4x4 INT Systolic Architecture Based Accelerator for Efficient Matrix Multiplication
Welcome to the documentation for the 4x4 INT Systolic Array Based Accelerator designed for efficient matrix multiplication.
This documentation is organized into the following sections:
User Guide
Everything you need to use the chip — setup, input/output formats, ready-valid protocol, and basic simulation instructions.
Go to User Guide
Developer Guide
For engineers and students who want to understand or modify the design. Includes design principles, internal modules, and detailed architecture.
Go to Developer Guide
TESTING
RESULTS
Repository
The full source code and Makefiles are available here:
GitHub Repository